The 2009 European Roadmap for design automation in semiconductor products (formerly known as the MEDEA+ EDA Roadmap), describes mainly "System on a Chip" (SoC) and "System in a Package" (SiP) products, taking the best of technology capabilities for addressing new markets. The 2009 edition mainly focuses on demonstrating a complete top-down design flow, starting at specifications, then System Level Design linking designers to formal customer's specification, parametrisable IPs creation, standards and Design for Manufacturability (DfM) supported by new TCAD (Technology CAD) developments.

It addresses specific needs, at particular points in time, and within a specific time frame 2008 to 2013 - from the current viewpoint of 2008. It will have to be revised and expanded with new ideas every year - such as technology CAD linked to Design for Manufacturability (DfM), Systems in a Package (SiP using new technology approaches such as TSV or Through Substrate Vias for 3D stacking), security and reliability (Dependability).

It is a living document that is intended to be a European forum with contributions from all. This is only possible with your active participation and endorsement. It will survive and grow with your involvement - so please continously send your latest inputs to the CATRENE Office in Paris.