ARTICLE APRIL 2002

Highlights from the 2002
"MEDEA+ Design Automation Roadmap"

Under the umbrella of the MEDEA+ Applications Steering Group, nearly one hundred of Europe's best design automation specialists from universities, institutes, semiconductor manufacturers and systems houses have prepared the 3rd edition of the "Design Automation Solutions for Europe" roadmap.

Focusing on the MEDEA+ mission of "Europe becoming a leader in System Innovation on Silicon", the new roadmap presents on 218 pages a strategic vision of the required electronic design automation (EDA) tools and methodology.

The Roadmap's main objectives are:

• to overcome - in line with the ITRS - the many existing EDA bottlenecks in System-on-Chip (SoC) development,
• to prepare the ground for integrated solutions in the relevant domains of the EDA design and verification flow.

And the expectations are:

• early validation of SoC specifications with the customer,
• decreased design time and cost,
• support in process engineering, through early product and process debugging, dynamic libraries developments and design rules validation for production.

What are the electronic design needs?

In the past, progress in EDA followed the process integration capabilities. It was based on individual initiatives, resulting in many narrowly focused design tools which are rarely complementary with each other.

Design flow cohesion and vertical integration across the different design abstraction levels therefore hardly exist. If that multitude of EDA tools is already inefficient today, it will become inadequate in the future.

For the design of systems-on-chip with 100 million gates or several 100 millions of memory cells, three basic problems have to be solved:

• How to be sure that specifications are in line with customer's expectations?
• How to manage the complexity in the design flow (hardware and software)?
• How to be sure that the detailed implementation will work?

At the same time, new ways to interface and collaborate on a world-wide scale have to be developed, as these EDA skills and resources will not be available in one single place, and the work will have to be shared by distributed design teams.

What does the "MEDEA+ EDA Roadmap" propose?

For its integrated top-down EDA solution, the MEDEA+ roadmap identifies the following main steps:

• Formal specification validation
• Functional architecture definition, resources selection (IP's) and architectural design
• HW-SW partitioning and scheduling
• HW-SW design, interface design and co-verification
• Integration (HW, SW, buses, wrappers?.)
• Physical implementation and test (including signal integrity analysis).

The present 3rd release of the Roadmap places particular emphasis:

• on system level design and specifications, where a significant amount of standardisation and development remain to be achieved,
• on implementation levels, where signal integrity (crosstalk, EMC, radiation tolerance) becomes a show stopper,
• on intermediate levels, where design automation, mixed analog and digital, testability and repair need improvement,
• on all levels for verification and test,
• on infrastructural level for concurrent engineering through distributed design data management.

The Roadmap postulates as "main breakthroughs" in top-down SoC design:

• More formal definition of the specifications of the SoC after validating the usage with the customer,
• Increased SoC design efficiency and optimisation-to-process by moving to higher levels of abstraction in the design flow. This requires the definition and propagation of constraints (handling both HW and SW),
• Standardisation of appropriate languages,
• Implementation of a flow with constraint propagation and verification able to handle SW, HW and IP reuse for both.

The Roadmap authors are confident that the guidance through the MEDEA+ Design Automation Roadmap will lead to a new design environment in which all these developments can be used in a unified flow.

This flow will rely on one appropriate object-oriented data base capable of handling constraint propagation down in the flow, with efficient reuse of the virtual components and with verification at all levels of the flow.

Specific contributions from EDA Start-ups

One chapter of the Roadmap is dedicated to the specific contribution from EDA Start-ups in MEDEA and MEDEA+.

SMEs and start-ups (e.g. ESTEREL (specif), TELELOGIC (SW), ADELANTE Technologies (synthesis), VALIOSYS (syst.archit), EONIC (embedded OS), POLYSPACE (software), COWARE (syst.archit), TEMENTO (test), MEMsCAP (MEM's above IC), METASYMBIOSE (verification), AVERTEC (formal layout proof), IROC (signal integrity), D & R (IP's), SCI-WORX (design) are almost all partners in MEDEA+ programme where they contribute to the development, engineering and commercialisation of advanced EDA solutions developed in the projects. Presently, they are the only channel for production of EDA tools in Europe.

Their products are very performing compared to competitors - with often a factor 10 improvement being reported on performances.

There exists a definite need to combine their available products in a coherent and parameterisable "design flow and database" environment so that a complete solution can be offered to semiconductors and systems designers.

The objective of the European participants in this domain is to take the lead in systems design for selected application areas, through strong co-operation between large IC suppliers, systems houses and specialised institutes.

It is only with such a vision that they will be able to reuse all the developments of the Universities, SMEs and start-ups in a common back-bone (based on the latest languages and communication standards) shared with the large EDA companies.