ARTICLE JANUARY 2003

System-on-chip devices to handle multiple inputs

Europe has an important global lead in the development of application-specific complete system-on-chip (SoC) devices. Through MEDEA+, the European microelectronics industry is seeking to maintain this leadership both through improvement in electronic design automation (EDA) to speed up production and in the development of a range of new features combining communications, display and storage in user-friendly consumer devices.

Increased device functionality inevitably leads to greater chip complexity. Advances in EDA technologies through several MEDEA+ projects are therefore intended to improve the reuse of intellectual property to speed development of new devices and reduce time to market. This has involved wider application of high-level design languages and open formats to enable the development of libraries of compatibly designed analogue, digital and radio frequency (RF) elements that can be combined easily into new designs.

For example, the MEDEA+ tools and methods for IP (TOOLIP) project A511 addresses European producers? demands for a seamless design flow for complex SoCs that exploits reusable intellectual property (IP) cores, system level modelling and verification techniques as the means of meeting these requirements. IP reuse is one of the most challenging aspects of electronic design innovation. It is essential to cut time to production for reliable, lower cost large-scale devices and to ensure European industry secures and safeguards leadership in the key Internet, digital consumer electronics and wireless communications markets.

TOOLIP is not trying to provide just another simulation tool but is developing a fully documented design flow with recommendations and guidelines based on state-of-the-art tools. New features, new semantics and new mechanisms for performance estimation of delays, throughput, and power consumption are being added. Consortium partners are also actively participating in defining and influencing international standards governing inter-company IP reuse.

The analogue enhancements for a system-to-silicon automated design (ANASTASIA+) project A510 set out to bridge the perceived gaps in the design process, with seamless top-down methods that include the tools and techniques needed to achieve a high level of automation and reuse. The objective is to eliminate the bottlenecks between system specifications and block-level circuit design. Development of automated modelling and sizing tools, together with reuse-oriented layout synthesis methods, will increase the reusability of analogue functional blocks ? markedly reducing design time and increasing design security. This will improve design efficiency and increase the probability of obtaining first-time-right silicon for SoCs.

Making platform-based design an easier and faster task is the next challenge. The specification and algorithm/architecture-co-design for highly complex applications in automotive and communication (SpeAC) A508 project set out to raise the level of abstraction at which creative work is performed. This has long been seen as the most effective means of improving design efficiency beyond that of the design flows currently employed in the microelectronics industry.

Such an approach is based on the idea that the next level above hardware/software co-design on predefined platforms should be specification, algorithm and architecture optimisation, as well as architecture generation. Project A508 combines two platform-based approaches: algorithm/architecture co-design, and component-based design for heterogeneous systems.

On the technology side, the technology-driven design and test for system innovation on silicon (TECHNODAT) project T101 is developing tools for automatic generation of data for basic cell libraries and embedded memory blocks, together with automatic validation possibilities that are not limited to a given technology generation. It also set out to guarantee the resulting chip works properly and stays operational in the field.

To decrease test times, project T101 addresses pre-silicon test program debug by virtual test engineering (VTE) for digital and mixed analogue/digital circuits. Partners also anticipate achieving much-improved implementation of the techniques involved in standards-based, multisite library development. While analogue and mixed analogue-digital systems are being used for an ever-growing variety of functions in all areas, design automation for the analogue elements has lagged behind that achieved for digital.

On the device side, MEDEA+ realised from its very beginning the strong convergence between terminals and consumer equipment ? from simple Internet terminals to broadband entertainment terminals with interactivity allowing video on demand.

For example, the secure pocket multimedia (Pocket MM) project A207 set out to offer an innovative MPEG-4 compliant toolbox solution for mobile handheld devices. This includes a user-friendly communication capability with very high audio and video quality. The toolbox contains a subset of the tools offered by the MPEG4 video compression standard and can be enhanced by adding new tools for digital rights management or other applications.

The MEDEA+ integrated modem for digital terrestrial TV (IM4DTTV) project A203 is focused on the transition from analogue to digital broadcasting ? a major topic in the TV industry, where interest centres on the provision of interactive services.

In Europe, the new DVB-RCT standard specifies an interactive return channel via cable, satellite and terrestrial networks. Project A203 is therefore designing and testing an SoC solution for an integrated terrestrial modem based on this standard. This low cost wireless technology will be able to penetrate markets that are currently poor in cable infrastructure, offering a major market opportunity for European suppliers. The project partners are providing a first generation silicon solution and a complete hardware validation platform covering all aspects of the DVB-RCT-based system, including both user terminals and broadcasting base stations.

The exponential growth in communications ? especially mobile devices, the convergence of PC and consumer electronic products, the quest for static and portable digital video capability, and the emergence of home servers (residential gateways) ? are creating a continuously increasing need for mass data storage. The future storage (FUST) project A202 is strengthening Europe?s ability to deliver innovative SoC devices operating with both optical and magnetic storage media.

As well as devising common system architectures, the partners in A202 are developing prototypes of key components, creating tools for testing and validation, and contributing to the format standardisation debate. Know-how acquired as a result of this initiative will stimulate growth in the professional and consumer electronics sectors. It could even lead to the emergence of completely new product types.