NEWSLETTER OCTOBER 2003

ELECTRONIC DESIGN AUTOMATION CRUCIAL TO EUROPEAN MICROLECTRONICS LEADERSHIP

Second quarter (Q2) revenue figures for the global electronic design automation (EDA) market showed an increase of 8% over the same quarter in 2002 according to the EDA Consortium. Is it an encouraging return to worldwide growth? Not yet worldwide. Some regions, like Asia-Pacific, are showing substantial growth, spendings in Europe however are lagging behind.
Investment in EDA is crucial to the future of the European microelectronics industry. While our manufacturing assets may be world class, our design automation resources have lacked engineering and performance maturity, resulting in a bottleneck that could prevent Europe exploiting the full possibilities of current and future silicon processes. For this reason, European microelectronics research programmes from JESSI through MEDEA to MEDEA+ have focused on developing knowledge and expertise in design automation.

Sub-micron silicon technology productivity is currently growing at some 61% a year, yet IC designer productivity is increasing at only 21%. This gap must be closed to meet the demand for ICs in mass-market consumer applications ? from mobile phones and automotive electronics to home networks and high bandwidth entertainment systems.

MEDEA+ projects are responsible for a number of EDA breakthroughs and are increasingly using the top-down design approach that is essential to make the most of system-on-chip (SoC) devices. The latest edition of the MEDEA+ EDA roadmap, released in mid 2003, identifies three areas on which Europe must focus to improve performance:

1. Accelerating process maturity to reduce time to volume production by increased automation in library production, faster product design and designing for manufacturability;
2. Speeding up high-quality chip design by formalising the dialogue between electronic systems manufacturers and their chipmakers; and
3. Making better use of intrinsic silicon capabilities, particular in very deep sub-micron (VDSM) processes for SoC.

Major efforts are required to meet these challenges, specifically:

• Design automation technology must be consolidated through greater reuse of hardware and software intellectual property (IP), hardware/software co-design and VDSM back-end verification;
• A ten-fold improvement in design efficiency and debugging must be achieved through the establishment of system-level design solutions ? including system specification, capabilities for early prototyping, usage studies and system specification validation;
• Targets must be established for one-month design cycles in silicon system platform solutions covering specific markets where most of the available software IP developments can be reused;
• Greater engineering effort must be put into design automation for manufacturability of hardware and software, similar to the improvements already obtained in silicon processing, and
• The latest standards for programming languages, design flows, single data model databases and IP must be exploited quickly to focus developments.

The MEDEA+ design automation conference being held in Stuttgart from 4 to 6 November as part of the European EDA Week will reflect on the role EDA must play to increase the competitive position of the European microelectronics industry. It will present innovative results from key MEDEA+ projects in the area of application-oriented SoC design ? including mixed digital and analogue/radio-frequency chips, system level specifications, programmable SoC, embedded SoC software and integration of the design flow.

Results will also be discussed in the context of the updated MEDEA+ EDA roadmap, part of the overall effort of MEDEA+ to reach adequate design efficiency and maturity for all the design steps between system level specification and signal integrity solutions.