The goal of this project is to allow designers to get the best benefits of the new technologies (down to 0.07µm) by development of automation methodologies and tools for Standard Cells and Embedded Memory development, for testing and for Design Techniques.

General goals of the project are to enhance the design reliability and the design efficiency of ASICs and to develop and verify methodologies based on simulation for the protection of ASIC designs from damage caused by electrostatic discharge and from undesirable substrate effects.

The goal of this project is to allow designers to get the best benefits of the new technologies (down to 0.07µm) by development of automation methodologies and tools for Standard Cells and Embedded Memory development, for testing and for Design Techniques.

This decade will mark a new trend in vehicle electronics. Total power consumption of a typical car rose from a few hundred Watts in the 1960s to around 2 kW in 2000, and the growth is expected to continue. Current 14-V battery systems are no longer adequate to meet this demand. A further increase in the electrical current would result in unacceptable thermal losses, and in additional wiring weight and volume - so higher voltages are essential. Standardisation activities are focusing on an increase the voltage supply of the electrical generator to 42V, charging a battery that works at 36V. The objective of the MEDEA+ SC 42V AUTOMOTIVE project (T122) is to determine which state-of-the-art semiconductor processes can support advanced system designs for this new generation of battery systems.

Embedded non-volatile memory, low-cost custom programmability and built-in analogue functionality will be essential requirements in future deep-submicron system-on-chip technology for many applications. Process technology advances being explored in the MEDEA+ CRESCENDO project (T123) will lead to realisation of the advanced SoC solutions needed in fast-growing sectors such as microcontrollers, cellular communications, smart cards, multimedia, automotive electronics and data storage for audio/video. A consortium including Europe's top three semiconductor manufacturers is developing high density electrically erasable programmable read-only (EEPROM) and flash memory - as well as low-cost, low-density programming elements, in 0.18 and 0.12 µm generation CMOS technologies.

Electronics capable of functioning under severe environmental conditions are increasingly required for in-car systems and other demanding applications, where semiconductor chips must operate at temperatures up to 200°C and beyond. At the same time, European car-makers are seeking to cut costs by building and testing engine and transmission assemblies with all the electronic control devices in place. That can only be achieved if the components are mounted directly on the unit, where they will be subjected to long-term extremes of vibration and humidity, as well as elevated temperature. The primary technical goal of the MEDEA+ HOTCAR project (T124) is to achieve and demonstrate robust system-level solutions to meet such needs. It is pushing the results achieved by earlier projects to a new level of exploitation by focusing on system-on-chip (SoC) solutions, state-of-the-art microchips and other increasingly complex integrated circuits (ICs).

Goal of the project is to develop advanced physical processes, design and validation methodologies and CAD flows for design and production of embedded memories (SRAM, DRAM, MRAM). It will therefore contribute to the competitiveness of Europe in three areas: System-On-Chip, CAD tools and electronics.
The main challenges are demonstrating the feasibility of a promising type of RAM (magnetic RAM); reducing the cost of embedded memories (through increased density and yield); maintaining high levels of memory robustness despite increasing error sensitivity due to miniaturisation; and diversifying of the memories offered in terms of speed / consumption trade-offs.

Transistor downsizing is proceeding faster than originally forecast. True 100nm technology is expected to arrive in 2003, soon to be followed by a 65nm generation. Various new materials and process technologies are currently under investigation, but no clear consensus has yet emerged on precisely how the coming chip generations will be manufactured.
The MEDEA+ T201 project team aims to influence the industry direction by achieving full 100nm integration, validated with a very powerful demonstrator chip that will comprising more than 54 million transistors, 300 million contacts/vias and some 9 km of interconnections. In addition, the partners will employ an innovative metal organic chemical vapour deposition process to develop advanced gate modules incorporating high-k dielectrics for devices of the next technology nodes at 65nm and below.

Mobile telephony is the driving force in the market for radio frequency (RF) integrated circuits. Generally accepted forecasts indicate that the number of cellular telephones sold will exceed one billion in the near future. There is a constant demand for ever-higher bandwidth and transmission rates - from 2.2 GHz for UMTS (universal mobile telephony system), to 20 GHz or more for future systems. While CMOS has become the main process in the semiconductor industry over the past decade, BiCMOS is rapidly gaining ground for higher-speed mixed RF-analogue chips. At the same time, silicon germanium (SiGe) technology is being promoted as the cost- and power-saving replacement for gallium arsenide (GaAs) in tomorrow's devices.
The goal of the MEDEA+ ASGBT project (T204) is to develop SiGe bipolar and BiCMOS technologies for cost-effective production of ICs for portable terminals handling voice, image and data transmission.

The first goal of this project aims at the development and characterisation of Partially Depleted CMOS Silicon On Insulator 120 and 90nm Technologies with copper interconnections for Low Power logic, RF wireless and therefore at the optimisation of the SOI process and SOI substrate to handle HF applications. Active and passive devices modelling and DC, AC and HF characterisation will be developed. Logic, analogue, mixed and RF low power blocks will be designed and characterised to demonstrate the technology suitability and to evaluate the impact of SOI specific effects on circuit performances. A further goal of this project aims at the development and characterisation of Ultra Thin Silicon films and Thin Box wafers (200 and 300mm) and specific process modules to demonstrate the capabilities of Fully Depleted CMOS SOI for future sub 90nm generations.

The goal of the project is the development and integration of a full CMOS logic process in a 300mm wafer diameter manufacturing facility.
The project targets the design and manufacturing of demonstrators representative of 65nm design rules. Another important goal of the project is to optimise and implement in the CMOS process, enabling techniques, allowing to achieve the 65nm node specifications on worldwide competitive 300mm European industrial equipment.

The growing complexity of integrated circuits and the trend to build complete system-on-chip (SoC) architectures are placing demands on semiconductor manufacturers to provide ever tighter incremental gate spacing. As device dimensions decrease, however, the sensitivity to small defects and impurities caused by the production process increases. The MEDEA+ 0.1 µm Fab project (T301) brings together leading European semiconductor manufacturers and their equipment and material suppliers to develop fabrication technologies for the reliable production of silicon chips with feature sizes down to 100 nm and below. The project is split into two parts, one covering the improvement of material purity for the next two generations of IC technology, and the other the development of relevant hardware to be used with the new production materials.

As the scale of CMOS transistors shrinks to gate lengths of 100nm and below, chip manufacture will require dielectric materials capable of being applied at extremely low thicknesses, while still minimising leakage current and giving good interfacing to other process layers. In the MEDEA+ ALAD1N+ project (T302), major European semiconductor manufacturers are participating in research to extend earlier exploration of breakthrough Atomic Layer CVD™ (ALCVD™) technology that allows controlled deposition of very thin multilayers with the necessary characteristics. Processes and equipment are being developed for gate dielectrics and gate electrodes, as well as for barrier and seed layer deposition in dual damascene structures of inlaid metal interconnects. Initial investigation of ALCVD processes for inter-poly dielectrics is also planned.

As semiconductor manufacturing technologies advance, traditional approaches to annealing the wafers used in chip fabrication plants are approaching their technological limits. The partners in the MEDEA+ CLASS project (T303) are therefore developing a prototype tool that is a major advance on existing methods. This offers faster heat-up and cool-down rates, combined with simplicity of operation, high wafer throughput, excellent temperature uniformity and low power consumption. While the system is already capable of handling 200mm diameter wafers, work is in hand to develop its capabilities for 300mm substrates, which will make it possible to produce more than twice the number of ICs per wafer for the same investment in staff, machines and floor space. Three types of process are targeted: annealing of shallow ion implants ('spike annealing'), annealing of silicides and rapid thermal oxidation.

The project aims at developing and providing a European source for (integrated) metrology and automation to keep up with the future IC process characterisation and control requirements. Therefore, various novel metrology concepts will be researched and developed aiming at making suitable metrology tools available at each "node" on the ITRS roadmap. Linked to the integrated metrology concept, a special attention will be paid to clean wafer handling concepts and (fab) logistics.

This project aims at providing the Integrated Circuit industry with a complete and thorough solution for the test of Radio Frequency products, both for their digital and analog parts. It will therefore offer the IC founders, and through them the whole Electronics industry, a means of improving the quality of their products while keeping their cost at the lowest possible level. The benefits will be passed on to the citizens, as consumers, by way of high performance low cost Information Technology devices.

Goal of the project is to investigate a full solution for 157nm: a photolithographic tool, reticules, resist and a process including the required special materials.

Integrated circuit feature sizes are forecast to shrink to 45nm and below before the end of the decade. By this stage, the industry's mainstay optical lithography process will have reached the fundamental physical limits of its refractive optics. Of the several replacements currently under consideration, extreme ultraviolet (EUV) lithography is strongly backed by many key players as the most likely successor for volume production. EXTATIC (T403), one of a cluster of EUV-related MEDEA+ projects, aims to develop a new reflective optical system operating at a wavelength of 13nm, and to provide the first EUV-exposed 300mm wafers for evaluation. By maintaining a lead in this crucial technology, Europe could capture a substantial share of an equipment market predicted to be worth € 10 to 20 billion within the next few years.

Lithography development is key to the continued advancement of the semiconductor industry but the cost of a totally new solution could approach € 1 billion. It is therefore essential to narrow the options and achieve a consensus on affordable 'post optical' technology. The annual International SEMATECH workshop indicates that extreme ultraviolet (EUV) lithography is the main candidate. EXTUMASK (T404) is one of several related MEDEA+ projects addressing various aspects of the need to develop a complete process to make the masks required for reflective EUV exposure at 13.4nm in an industrial environment. To achieve these results, a whole new multi-sandwich structure is being specified, materials and coating techniques developed, and appropriate metrology tools designed for monitoring the process and its final results.

Extreme ultraviolet (EUV) lithography is the leading contender as the core process for production of integrated circuits with features as small as 50nm. A critical issue is development of a source able to emit radiation at the very short wavelengths required for new optical systems. The T405 EUV Sources project, part of a cluster of EUV projects within MEDEA+, brings together a consortium of 13 European organisations to assess and select from two approaches - electric discharge and laser-excited plasma. Each has its advantages and disadvantages but neither has so far demonstrated sufficient reliability and resilience to permit commercial introduction. As well as investigating the alternative technologies, the initiative is establishing a development roadmap to enable follow-on projects to focus on device manufacture using the most promising route. This will help maintain Europe's lead in lithography technology over US and Japanese competitors.

The EXCITE project aims at developing Extreme Ultra-Violet (EUV) imaging capability for the 45nm technology node and beyond.
In order to achieve this goal, a project was defined in which all aspects related to EUV lithography will come together to enable 45nm technology node patterning capability on a full field alpha-tool by year-end 2005. The project has close links to other EUV based European projects, of which EXTATIC and EXTUMASK, developing the alpha-tool and EUV mask infrastructure, respectively, are the most important.

Goal of the project is to demonstrate feasibility of a new maskless lithography concept for high throughput patterning at 45nm by means of a system Demonstrator.
After proof of principle, development of a prototype can be initiated.

The aim of the project is the development of a novel projection technology for Mask-Less Lithography targeting the low and medium volume devices fabrication including fast prototyping. Main goal will be the development and realisation of a proof-of-concept tool for the 45nm technology node. In parallel feasibility of the concept for application in advanced beta tools will be investigated.

Goals of the project are to develop novel design methods, production concepts and qualification tools for next generation of micro-modules and micro-components using highly integrated ICs and multi-layer substrates. This will be accomplished by using advanced high-density packaging technologies to enable new platforms for low-cost mass products to be used in next generation telecom and automotive applications.