Power Amplifiers aNd Antennas for Mobile Applications More info
The project focuses on future multi-band, multi-mode more efficient Power Amplifiers and Transmitter systems covering: integrated systems, discrete systems and distributed systems (collocated with antenna) applied to a set of target applications: cellular handsets (3/4G, mmWave) and Base Transceiver Stations (BTS) (3/4G), Avionics, mobile Satellite communication (Satcom) and home networking as well as specific Base Transceiver Stations, and addresses Software Defined Radio (SDR) roadblocks in order to assess at system level the PANAMA advances. Main common target is an efficiency gain for each application: 20% compared for integrated systems, 30% for discrete systems and 10% for distributed systems.
The objective of the HERTZ project is to enable energy savings in homes of consumers via energy efficient home networks by providing home energy control systems. This requires three elements: • Notion of context, based on sensors; • Control of equipment that consume energy, such as lighting and brown goods; • Connectivity between sensors and equipment, realised through a wireless infrastructure.
Computing Fabric for high performance Applications More info
Hardwired SoC architectures suffer from a lack of flexibility regarding market evolution, resulting in an excessive design cycle time and increased cost. Furthermore, process variability is not yet well addressed for 32 nm and beyond. The objective of COBRA is to develop and experiment an open, flexible and high performance platform by substituting heterogeneous hardware/software subsystems by a regular array of processors. The platform will be driven by Telecom, Video and Multimedia benchmark applications and demonstrated on 32nm silicon with 3D stacking.
Coexistence Of RF Transmissions In the Future More info
This project aims at developing new HW and embedded SW devices that will fully comply with the next wave of computing and will fully integrate in both “ambient-intelligence” and “internet of things” scenarios. More precisely, the project will develop, prototype and experiment with new ways of establishing high-speed, secure bidirectional wireless communication channels and supporting new, intuitive and simple context-sensitive interactions between persons and objects belonging in the environment. Furthermore these interactions will by necessity preserve both the security and privacy of the transactions.
High Dynamic Range – Low Noise CMOS imagers More info
To address societal needs in the areas of healthcare, entertainment, and road & industrial safety. This project will lead to a number of societal benefits: higher efficiency, less errors in medical diagnostics, change from treatment to prevention; enhanced experience for TV viewers by unprecedented image quality; an additional pair of “automatic” eyes on the road; see more in a dark environment, improved recognition capabilities; improved safety and flexibility of assembly lines to safeguarding man and machine. Research topics are pixel design and modeling, low-noise analogue read-out including ADconversion and multiplexing, modeling of thermal-, optical- and electrical cross-talk, optics and correction algorithms for CMOS imager and optical enhancement. Of the many performance aspects of a CMOS imager HiDRaLoN will focus on increasing the dynamic range to 120dB and lowering the noise level with at least 50% to make CMOS imagers surpass today’s CCDs.
OPTImisation of MItigations for Soft, firm and hard Errors More info
This project aims at developing optimised mitigations for advanced digital and power electronic systems in order to solve the major issue of their reliability against the increasing problem of soft, firm and hard errors. The expected deliverables are a set of validated mitigation techniques from layout to applications architecture levels, customised mitigations for given applications and a strong effort in standardisation. The expected benefits will be the capability to use advanced electronics in critical end-user applications, and ensure reliability of consumer electronic, especially for low power.
ICAF aims to research, develop, and demonstrate future image capture, processing and transmission technologies for Machine Vision (MV), Security/Surveillance and Professional Broadcast (PB). The specific technologies that will be researched are: • Increased pixel rates (36 Gbps for Machine Vision and 1080p180/i360 for Broadcast) • Increased pixel sensitivity (over a wider spectral range) • Single lens 3D capture • Computer hardware technologies in Broadcast and Machine Vision. • The research will cover optics, CMOS imagers, new 2D and 3D denoising algorithms, 2D and 3D image processing algorithms, new video transmission ICs, video compression, Video over Internet Protocol, frame grabbers (MV), compliance recording (PB), and video camera application designs.
This project aims at developing highly efficient, integrated and reliable power electronics technolo-gies for automotive, aeronautics and healthcare applications (Magnetic Resonance Imaging systems). The project covers the development of new technologies for discrete power components (IGBT’s, JFET, Diodes, based on wide band gap semiconductors), power cores, storage elements (supercapaci-tors), packaging for high temperature, thermal and EMC management solutions.
Design for RELIABILITY of SoCs for Applications like Transportation, Medical, and Industrial Automation More info
This project’s goal is to ensure system reliability by means of combination of design solutions for future complex SoCs as needed in applications like transportation, medical, and industrial automation. SoC complexity is rapidly increasing due to integration of new functions, devices, sensors/monitors and extended operating conditions. This and the shrinking dimensions of SoCs make them increasingly prone to failure.
COmmunication-centric heterogeneous Multi Core ArchitectureS More info
Aims at breakthrough low-power design solutions for (data) communication-centric heterogeneous multi core architectures targeting 45nm and 32nm CMOS technologies. These architectures will be exploited in a number of future applications e.g. the next generation of programmable multi-processor mobile phones and mobile digital entertainment devices. COMCAS investigations concern the complete low-power design hierarchy looking at all aspects from system level choices, modelling of applications (algorithms, protocols) and architectures, maximize the reuse of existing IPs using the most appropriate tool chains, partitioning and mapping, cycle-accurate and bit-true virtual prototyping, minimal power design blending semi- and full custom circuit designs at transistor level in technologies of 45 nm and beyond.
3D Integration for Multimedia and Mobile Applications More info
The projects aims at providing novel system methodologies, new design tool & system architecture solution to handle emerging 3D integration technologies for multimedia & mobile (M3) product. The 3DIM3 project will therefore enable the design, from system and architecture level to layout, of 3D integrated M3 products with higher performances, lower consumption smaller size/form factor at lowest cost.
Perishable mAnagement through Smart Tracking of lifEtime and qUality by RFID More info
This project aims at exploring and developing RFID-based sensor platform technology, which will be demonstrated in an intelligent package monitoring the environmental conditions of perishable goods in the supply chain between production and consumer and therefore guaranteeing a more effectively product's quality. The Pasteur project thereby addresses the need to increase on-line knowledge on the traceability of individual products and the demand to increase the accessibility of the information about these products for the consumer end-user. Key differentiators in the technologies to be developed are ultra-low power and extreme low cost.
Renewed Embedded Flash and other Innovative NVM for Extended Domains of application More info
The REFINED project aims at ensuring the continuation of Europe leadership in the field of embedded non volatile memories. This leadership keeps European leading position in some areas like smart cards and to boost European participation to large markets like consumer and automotive controllers. It brings together the main European R&D actors (semiconductor companies, research laboratories), in order to develop the 65 nm generation as well as improvements to the current 90 nm generation (shrink version). The base for the next generation is also set along evolutionary approaches as well as more radical ones. Essential issues of reliability, testing and IP development are addressed in parallel. The REFINED project aims to create fully integrated technology platforms for the embedding of NVM functions in sub-90nm CMOS technologies (process, demonstrator, test and reliability infrastructure) and in parallel to setup low cost effective solutions for qualified technologies.
UlTimaTe Enablement Research on 32/28 nm MOS Techn More info
UTTERMOST objective is to transform an initial 32nm research into a full fledge Technology Platform enabling design of IC products and their cost effective manufacturing in Europe. The main goal of the UTTERMOST project is to develop advanced process modules, and validate a design platform (design kit, models, and libraries) for reliable and manufacturable digital CMOS 32nm and 28nm technologies on 300mm wafers in the 2 European manufacturing facilities of Crolles for STMicroelectronics, and Dresden for GLOBALFOUNDRIES. The goal of UTTERMOST partners is to make 32/28nm digital technology available for design and industrial exploitation in Europe.
Chip-On-Chip technology to Open new Applications More info
This project aims at developing a complete mature 3D integration technology platform covering the entire range of processes required from vertical interconnects (TSV, micro bumps…) and robust bonding to innovative packaging approaches to address a wide range of products. The main objectives of this project is to achieve chip-level three-dimensional (3D) TSVintegration, Wafer-to-Wafer and Die-to-Wafer bonding, and packaging of stacked circuits, in order to create a complete technological platform for high performance and cost effective 3D systems manufacturing. The objective of COCOA project is to define a robust 3D integration technology platform covering the existing gap between medium (104 cm-2) and high density (106 cm-2) technologies, including packaging of two or more stacked layers.
REaserch on optimal ArCHitecture and INteGration of 22/20nm node core digital CMOS technology- Electrical proof of concept More info
The goals of REACHING 22 is to RESEARCH THE OPTIMAL ARCHITECTURE AND INTEGRATION FOR THE 22/20 nm NODE core CMOS technology and do an electrical proof of concept. Preliminary assessment work using FDSOI technology will be done, while in parallel the necessary process modules and an SOI substrate (UTBB) for the 20nm node will be developed. Subsequently an electrical benchmark comparison will be conducted between the bulk and the FDSOI 20nm CMOS technology architectures based on transistor performances and an initial design library evaluation mask set. The project will contribute to the European Industry reaching the 22/20nm technology, but also strengthen the position of the European Academics in the exploration of smaller nodes and the Beyond CMOS.
From RF to MMW and THz Silicon SOC Technologies More info
This project aims at the establishment of silicon technology platforms for emerging RadioFrequency, mm-wave and THz consumer applications, 77GHz and 120 GHz automotiveradars, THz Imaging and Sensing, 60GHz wireless networking and fast downloading Rx/Tx,100Gbit/s optical data communications and RF wireless communication requiring High performance devices (transmitted power, consumption, integration, isolation), as well as twoway satellite communication systems. The main target is to reduce cost while maintaining/enhancing the performance of existing solutions. Developments of two BiCMOS technologies are forecasted within the project. For ST this is a new 0.5THz 65nm SiGe BiCMOS platform. For NXP, the starting point will be a 0.25um SiGe/C BiCMOS technology improved to address mm-wave to THz applications. Apart of breakthrough in silicon BiCMOS technology, breakthroughs in microwave packaging and Built in Self Test applied to mm-wave and THz will be studied.After optimization, characterization of the THz component as well as MMW and RF ones will be conducted and models will be adapted and model parameters extracted. Design Blocks will be developed both for full function integration and for DFT or BIST introduction and full demonstrators will be carried out together with exploration of some advanced promising applications.
EXtreme uv lithography Entry Point Technology development More info
The goal of the EXEPT project is to develop technologies, tool& infrastructures components as required for high volume EUV lithography for 22nm node in 2012.The project aims with the expected introduction of EUV lithography in high volume semiconductor production lines at opening new business opportunities for the participating companies.
Test is the last chance to deliver quality and reliability to the end customer. A leap forward is required to incorporate test as a mindset in the total product creation. The TOETS project has the ambition to create this breakthrough in methods and flow used by the test technologies by considering test in the WHOLE value chain from design to application.
Development of 450 mm SOI substrates, related technologies and equipments More info
The goal of the project is to develop 450 mm SOI substrates and related technologies in order to bring equipments and substrates at a mature level for industrialization. The project will include tool development and SOI implementation, with feasibility milestone followed by start of a pilot line. SOITEC will lead the consortium of key equipment suppliers (EVG for bonding, Mattson for RTP), supply chain suppliers, three institutes for the evaluation of tools and technologies and IC maker Intel.
NGC450 project aims to enable in Europe the development of sub modules (for process or metrology) around a wafer handling platform, dedicated to support the 450mm wafer size migration. The project will be conducted in 2 steps: • Development of a wafer handling R&D platform. • Integration of standard base process modules into the platform. The developments will be performed in compliance with the standards and specifications being already settled by ISMI, and will also be in line with the delineation of both CATRENE and ENIAC projects definition. This synergy between the European companies is expected to fasten the development and reduce costs by sharing the efforts as well as the risks. The modules and equipments resulting from the above mentioned developments will be made available and valued for a worldwide utilization, upon each European partner agreement and convenience. The developments will be driven with the objective that part of the technology improvements will be applied to 300mm in order to sustain the competitiveness of European semiconductor Industry who work on 32/28 nm and below (22/18 nm).
Autonomous Nine Degrees of Freedom Sensor Module More info
The project 9D-Sense aims at an autonomous integrated 9 degrees of freedom sensing module and will therefore develop technologies for sensing itself, energy harvesting, energy storage and wireless communication. A small-sized and heterogeneous integrated system is addressed to enable cost competitive solutions in the fields of consumer and health care applications. Extreme energy efficient technologies will be developed and applied. Central goal is building prototypes of the sensing system as well as their testing and proof of functionality in dedicated application environment.