The project targets the design of scalable, hybrid high-performance embedded systems and computing systems whose macro-architecture will mix general purpose processor cores and more dedicated accelerators including GP GPUs and programmable logic.
This general goal positions SHARP project as advanced developments to make the convergence of the parallel computing models of cache-coherence, message passing and streaming, the ultimate goal being the design of high-performance embedded systems and extension of existing high-end server platforms like HPC with a large range of computing accelerators.

This project aims at developing an Open Platform to provide integrated home applications to the consumer mass market.

The project aims at studying and setting up an end-to-end 4K Ultra HDTV chain (broadband and/or broadcast) for use at consumer premises and/or at dedicated show-points. The required bandwidth and activities over the chain being at least 4 times more than for full HDTV, the main challenges here are to study and develop ICs implementing new codecs more efficient in term of bandwidth with improved and additional features.
The project consortium is composed of partners over the value chain, from content creation to display at home, including IC vendors and academics very active in the standardisation bodies.

The goal of HARP is to develop an architecture which can be optimized for a given customization level. HARP will associate on the same SoC: a homogeneous array of processors, specialized processors and hardware IPs. Then, HARP will validate this customizable heterogeneous design platform on different application fields (Video, Smartphone, Aeronautics and Automotive). Design productivity will benefit from a unified hardware/software design flow. Data flow programming models and reconfigurable memory hierarchy will allow designing high throughput, fault-tolerant applications.

The WiCon project will provide low-cost, highly-integrated system solutions for galvanic connector’s replacement in the consumer and industrial market segments. Smart electronic systems for data and power transfer will be demonstrated, exploiting ultra-low-power point-to-point mmWave connections and optimized power transfer technologies merging NFC with wireless charging applications. In addition, polymer waveguides carrying mmWave signals for data-transfer rates above 20 Gbps will be demonstrated, as a low-cost replacement option for expensive optical components in the next-generation 10Gbit USB standard and above.

The CORTIF project aims is intended to at optimise the coexistence concurrent exploitation of radio frequencies by multiple communicating devices in a world where there are increasing demands on available RF spectrumof concurrency frequencies bands. It is applicable across distances of different orders of magnitude; from a single PCB out to the wide area with radios that might be far apart. CORTIF will exploit the trade-offs that are possible by working across layers of the communication stack and will address both the application and technology layersIt applies to both the application level and the technology level;. Mobile, Set-Top Box and TV makers will define the system requirements constraints; semiconductors suppliers and integrators will develop the coexistence techniques strategies taking into account considering the RRF standardization activity, the power consumption, permissible error rates and, of course, the bill of materials. Assembling such a wide range of expertise from application developers to semiconductor designers, standards experts to software developers, is only possible in a large, multi-national, multi-specialism project such as that enabled by CATRENE.

The NewP@ss project targets the development of advanced (microelectronics and embedded SW) secure platforms suitable for the coming of new e-Passport generation currently under discussion at the ICAO (hence usable and recognized as approved travel document at European and International level) but which could also be used for hosting dedicated e-services applications of both government and/or private nature.

The general objective of the MobiTrust project is to develop a complete embedded framework (HW, SW mechanisms and related management, HW/SW forensics tools) aimed at enhancing the security and privacy protection of future mobile platforms such as smart-phones or Tablets running over open platforms such as Android or Win8. These mechanisms will target primarily new usages of such devices, supporting some major trends in enhanced mobility both in the Consumer/Enterprise (BYOD), Smart-City and Civil Security, Mobile Cloud, Massive On-Line Open Courses (MOOC).

Future Fully Electric Vehicles (FEV) will imply huge design challenges for electric and electronic components. The close vicinity of high field strength from high power cables and electric motors and sensitive high density electronics requires a holistic approach concerning electromagnetic compatibility, respectively electromagnetic reliability (EMR).
To make this more worse the commonly used shielding effect of the car’s metal case will disappear due to lightweight designs, using carbon fibre cabinets. The introduction of the electric power train establishes voltage and power levels into the vehicles, which were previously not dealt with. The voltage increases, depending on the concept, by a factor of 10 (20 dB) up to approximately 100 (40 dB). The situation for power is similar. It must be concluded that future EMR behaviour of new communication units (e.g. intelligent assistant systems for range extension) in EV requires a significant reduction of electromagnetic emission generated by the electric power train components.
The project EM4EM tackles these problems and works out their solutions. The initial priority is to determine all sources of interference and critical couplings and to quantify their disturbance potential. New design methods, tools as well as measurement and test procedures which fulfil all requirements for electric vehicles, will be developed. Finally a full set of models and simulation tools for an integrated virtual process will be available. Reliable components and systems for light-weight and compact electric vehicles will be the result. The gained information will be used for better processes and products of the partners and be published in order to design competitive and innovative products in Europe. Therefore significant design flexibility will be achieved. Finally the performance of the developed concepts will be presented on the basis of three demonstrators.
Therefore three levels of demonstrators are foreseen to validate the EM4EM project results (Level 1: low level demonstrator with simple cables and ground planes (Cable Harness + Power Modules + Control Units (IC/Sensors); Level 2: intermediate demonstrator with a real car body and EV subsystems; Level 3: complete demonstrator based on existing EV versions (test car). This approach is unique and will be managed only in close cooperation with all EM4EM partners.

(Best ENergy EFficiency solutions for heterogeneous multI-core Communicating systems) is a cross-industry research & development project consisting of 19 organizations including industrial, SME and university partners from France, the Netherlands, and Portugal. The project is labeled within the framework of CATRENE, the EUREKA cluster for Application and Technology Research in Europe on NanoElectronics.

Heterogeneous-INCEPTION aims at offering European companies a powerful system-level design methodology and a unified simulation framework to build multi-domain virtual prototypes to efficiently and effectively design and verify Cyber-Physical Systems (CPS) including computational units, bioelectronics, thermodynamics, mechanics, etc.
To achieve this “Dreams within Dreams”. H-INCEPTION will drive the OSCI SystemC AMS and Accellera IP-XACT standardization by contributing language extensions and dedicated solvers for multi-domain system modeling and analysis. Targeted applications encompass automotive (safety), communications (connectivity, energy) and biomedical (healthcare).

The OpenES project will address IP and subsystem specification, modeling, integration, packaging, and code generation from abstract system-wide specifications to architectural models with truly mixed HW/SW components (application software, hardware-dependent software/firmware, analog/digital HW) and their validation/verification based on virtual prototyping platforms. For the first time these platforms will support also extra-functional properties like power reliability (extendible for further ones) and support a design methodology based on application use cases. This will enable system designs of higher complexity and functionality as they will come with future SoCs and SiPs, increased design productivity, less design errors and less re-designs, and faster time to market. In OpenES, major European semiconductor companies and innovative big European system houses (dependent on tailored ICs of highest functionality) collaborate with leading Universities/Institutes and IP and EDA tool vendors, subsystem providers, to define, develop, and validate advanced virtual prototyping technologies and contribute to open standard recommendations. To prove the applicability and effectiveness of technologies, flows and recommendations, developments will be validated in Proof-of-Concept Demonstrators (PCDs) based on industrial designs and their associated applications.

The next devices in the Mobile Wireless roadmap will need to address the LTE-advanced transfer rates (more than 100 Mbit/s) and need to give access to the multimedia contents with no latency to the user. To target both objectives at the same time ST-Ericsson has decided to embark the 2 functions in a single chip called “NOVATHOR™”. The rapid increase of gates density will not sustain by itself the complexity of this kind of device. It is mandatory to go on the ITRS journey and to launch all necessary actions to prepare the next process node. DYNAMIC-ULP aims to develop advanced process modules, and validate a design platform (design kit, models, libraries) for reliable digital and memory CMOS 22/20nm technologies on SOI (Silicon on Insulator) in European manufacturing facilities (Crolles). For ST-Ericsson the goal is to get an efficient design platform for use by its European product divisions. FD SOI 22/20nm CMOS technology the first demonstrator is scheduled for Q4'13 and test & analysis of DFM effects in Q2’14. The absolute need to recover the dynamic range from 1.1 v (necessary to run at 3.25 GHz) and low voltage 0.4v (necessary to run long play) is carrying the essence of this project.

Three Dimensions Flex Fluidics, (3DFF) aims to develop a 3D designed sensor on flexible surfaces, enabling integration into a disposable diagnostic test, ie. low cost. The goal is to develop a digital drug screening test in saliva, which is intended to be compatible with digital mobile devices and count as evidence in court, without resorting to expensive additional test in the hospital involving blood sampling.
The second use of flexible chip is to detect D-dimer, substance secreted by the human body when it is experiencing a heart attack. This Digital Diagnostic of the Infarct will also be done with a disposable diagnostic test.

Electronic systems in cars and planes are becoming more sophisticated, and demand more integration and higher performance from semiconductors. However, it is well-recognized that technology scaling alone threatens the integration of highly reliable and safety critical products in scaled technologies due to the associated product lifetime degradation. Hence, this motivates the need for new reliability aware design approaches and solutions. The RESIST project targets reliability aware design methods and run-time adaptive approaches for next-generation resilient integrated electronic systems in Automotive and Avionics. The focus is on reliability, cost-effectiveness and quality of semiconductor devices. The consortium consists of semiconductor companies, SME’s, academia, institutes, and end users. Expected benefits are >2x more cost-effective resilience solutions, >25years lifetime of embedded devices, >20% higher component/integration density at the same level of reliability, and up to 30% reduced reliability testing costs. An early-warning system by health monitoring of system components will be developed.

The MASTER_3D project will contribute to transforming EU leadership in R&D of 3D Integrated Circuits into 3D IC manufacturing leadership. Manufacturing methods to maximize process robustness and yield, minimize ramp-up time, support high volume production and reduce manufacturing cost will be developed and implemented in the consortium FABs. The activities will focus on 3D ICs with Through Silicon Vias (TSV) and Wafer Level Packaging (WLP). Manufacturing Excellence will be addressed by: - tool enhancements to support high yield, mass production - novel 3D Wafer Parametric Test, Functional and Final Test concepts - Characterization and in-line Metrology methods development. 3D IC yield models allowing quantifying the impact of the different yield detractors will be developed and used to accelerate the learning curve.

EmPower has a clear goal to develop an innovative fabrication concept for high-power modules for e-mobility and industrial applications. This concept is based on chip embedding technology for thin IGBTs and diodes and an innovative double-sided wafer plating process and equipment for thin wafers. The radical innovation of the concept lies on double-sided cooling, vertical current and heat flow in order to drastically improve heat dissipation and the thermal impedance of the embedded power cores.